1. Field of the Invention
This invention relates to integrated circuits and particularly, though not exclusively to integrated circuits for use in single or multi-processor systems.
2. Discussion of Prior Art
One object of the invention is to provide an integrated circuit, (to be referred to herein as a “Butler Chip”) which is capable of directly supporting the shared data and multi-tasking concepts of real-time networks in the context of single or multi-processor systems.
A further object is to provide a more deterministic (in the temporal sense) execution environment so as to eliminate some aspects of pessimistic timing analysis at the fundamental level of computer operation.
For a better understanding of an application of the “Butler Chip” to be described herebelow, reference is made to our co-pending Patent Application WO91/16681 (now U.S. Pat. No. 5,469,549). Therein, two Central Processing Units (CPU) are able to interact through an Asynchronous Dual Port Memory (ADPM). The ADPM can carry many communications routes (spatially multiplexed) such that there is no temporal interference between these routes, and where the temporal interaction between operations at the two sides of the same route is confined entirely to that interaction which is implicit in the protocol which characterises the dynamic of the route.
The latter property is dependent upon the fact that the ADPM has two completely independent access paths to every memory element and itself applies no exclusion.
Support for the protocols of the multi-processor communications systems of WO91/16681 is provided by a Communications Executive Chip (CEC) which contains logic for many parallel routes of various types. Support for scheduling is provided by a Kernel Executive Chip (KEC) which contains the logic for controlling 64 activities organised in 8 priority levels with 8 activities in each level. Selection at each level is controlled by a round robin polling logic. The highest priority level can be stimulated from external devices, including the set of CECs associated with a CPU.
Both the CEC and the KEC are accessed as memory attached to a private bus of each CPU, with individual chip functions being associated with particular access addresses. This allows the KEC's and CEC's to be used with any type of processor.
A particular feature of the approach to the implementation of routes between activities in adjacent processors, concerns the way in which implicit stimuli are handled. A CEC can multiplex a number (eg 32) of stims (termed secondary stims) and can indicate to the KEC (by means of a “primary stim” that a secondary stim is present. It is therefore necessary to use software to unpack and distribute the secondary stims. In WO91/16681, this has to be effected by infrastructure software containing stim servers. Disadvantageously, this arrangement introduces temporal indeterminacy because the stim servers run and impede the progress of application level activities.